Hi,
I am using the JESD204B IP (subclass 1) on a Stratix 10 FPGA, to interface with a ADC32RF45 ADC.
The LMFS configuration is 8 2 8 20 and K=32.
The problem I am having is that lanes don't seem to be aligned. I had this feeleing when looking at the sinewave, and I confirmed it by setting the ADC in a test mode to generate a ramp.
I am seeing that all the lanes receive the initialization sequence at a different time (or at the same time) : K28.5 (0xBC characters) and then K28.0 (0x1C) to K28.3 (0x7C).
Whatever line they receive 0X1C characters first, compare to the others, will keep this delay forever.
Example :
In this LMFS config (8 2 8 20):
samples 0 to 4 are received on Lane0
samples 5 to 9 on Lane1
samples 10 to 14 on Lane 2
samples 15 to 19 on Lane 3
Let's consider only the 4 first lanes, in this example, Lane 0 has received 0x1c character (start of ILA sequence) one cycle before Lane 2 and 3. And Lane 1 has received 0x1c character 26 cycles after Lane2 and 3:
Now, this delay will be kept forever.
From my understanding, delay between lanes in something common, as it depend of the layout and the routing of the signals, but Elastic Buffer (RBD) should take care of aligning them.
What could cause this to happen?
Thanks
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