I am using the JESD204B core with an Arria-10 interfacing to AD9025 Madura ADC. The Subclass 1 link uses 2 lanes operating at 9830.4M.
What we see is that at normal room temp everything comes up fine and passes data correctly, however when the system is cooled to -20C on power up the deframer will stay in the CGS state and keep SYNCn asserted.
One thing we found was that if a working system (room temp) was cooled but not power cycled it would continue to operate correctly. PRBS measurement has shown that the link actually has a lower background error rate at lower temps, and even then only of the order of 50 errors over 10 minutes. This suggests the PCB links are actually ok
Any ideas what could be going wrong?