I'm using the Cyclone V GT development kit and have the JESD204B example design up and running. The example design uses 4 transceivers. My use case only requires 1 transceiver.
I've used the JESD204B IP generator to create a module with the desired LMF values. I have a testbench that loops the TX serial data back to the RX serial data. In simulation, the link becomes aligned but I see groups of 8 values repeated on the RX side. The source of the repeated data appears to be the av_hssi_8g_rx_pcs_rbc.sv module down within the transceiver module.
Which upper level modules from the example design can be used in a customized test case (1 transceiver)? The pattern_generator_top, pattern_checker_top, altera_jesd204_transport_tx_top (assembler) and altera_jesd204_transport_rx_top (deassembler) all appear to use parameters that would work with my configuration. The control_unit module I'm not sure about. What is the control_unit sending to the PLL and transceiver reconfiguration interfaces? What is the basis for the phy.mif that gets read in? If the phy.mif is specific to the 4 transceiver example design, how would I go about creating a new phy.mif for a 1 transceiver design?
Intel-PSG has already provided a script to run simulation in our Design Example generated using Quartus. Hence, for customized test case, you will need to reverse engineer from the library files used to identify the top modules.
The instructions to run simulation is available in our user guide (pg 41 onwards);
I was able to create a single transceiver test case using most of the components from the canned example design. Unneeded portions of the control_unit state machine were commented out (I did not need the SPI operations). Obviously, the JESD204B core itself had to be regenerated with my custom parameters. A key piece that does not get updated with the required parameters is the core_pll module. The following link provides a couple of important formulas to determine the proper core_pll settings:
It's disappointing that this key part of the JESD204B design is not handled by the IP generator. The PLL settings and the JESD204B IP are absolutely tied together based on the chosen parameters. You may still see rx_is_lockedtodata, dev_lane_aligned and the rising edge of sync even when the core_pll is configured improperly. Improper core_pll settings are what caused me to see repeated groups of bytes on the RX side.