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L- and H-tile Avalon® Streaming IP for PCI Express - x16 simulation

Anonymous
Not applicable
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Hello,

I'm trying to simulate an x16 L- and H-tile Avalon® Streaming IP for PCI Express.

Using: Quartus Prime Version 22.2.0 Build 94 06/08/2022 SC Pro Edition.

For this, both a Root Port and endpoint are instantiated and connected via the serial interface.

A 100MHz reference clock is provided and resets driven as described in the User Guide.

However, the ltssm never exits the Detect Quiet stage.

Interestingly, this is only the case when generating the IP Cores using 16 lanes. When using e.g. 8 lanes, the link training completes as expected and transaction layer packets can be sent from the rootport to the endpoint.

Hence my questions:

  1. Can two x16 IP Cores be simulated against each other using the serial interface? I.e. connecting rx_in/tx_out of the root port with tx_out/rx_in of the end point.
  2. Setting bit at index 0 of the test_in input port to 1b'1' supposedly "turns on diag_fast_link_mode to speed up simulation" according to the User Guide . This indeed causes the ltssmstate of the root port to walk through the link training sequence. Also one can observe transmission on the serial interface, supposedly PCIe TS1 and TS2 Ordered Sets for link training. However the state goes back to Detect Quiet after Configuration Complete. What does diag_fast_link_mode mean?
  3. Can two PCIe Streaming IP for PCI Express alternatively be simulated against each other using the PIPE interface?

Thank you in advance!

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wchiah
Employee
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Hi,


If the ltssm is stuck in detect.quite stage, You may refer to the Fault Tree Analysis table.

It probably cause by the Reset issue, Ref clock Issue

https://community.intel.com/t5/FPGA-Wiki/FTA-PCI-express/ta-p/735993


Also, based on my understanding, it is possible to simulate two PCIe IP using PIPE interface.

To simulate two PCIe Streaming IPs using the PIPE interface in Quartus, you would need to create a testbench that includes two PCIe controllers, each with its own PHY, and connect them together using the PIPE interface. You would then use the Quartus Simulation Tool to run the simulation.


Let me know if you need any further clarification on this.


Regards,

Wincent_Intel


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wchiah
Employee
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Hi,

 

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket

 

Regards,

Wincent_Intel


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wchiah
Employee
585 Views

Hi

 

We have not hear from you and this Case is idling. It is not recommended to idle for too long.

Therefore following our support policy, I have to put this case in close status. My apologies if any inconvenience cause

Hence, This thread will be transitioned to community support.

If you have a new question, feel free to open a new thread to get support from Intel experts.

Otherwise, the community users will continue to help you on this thread. Thank you

If you feel your support experience was less than a 9 or 10,

please allow me to correct it before closing or let me know the cause so that I may improve your future support experience.

 

Regards,

Wincent_Intel


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