10G LL Ethernet MAC: Newbie question on the timing diagram for the AVST TX Interface. In TX introduction, the user guide says: "The MAC TX receives the client payload data with the destination and source
addresses, and appends various control fields depending on the MAC configuration." And shows the Frame concept in a picture on page 37-38.
Then in the timing diagram (on page 43), the user guide is showing relation between AVST TX data and XGMII data interfaces.
Thank You in advance to anyone who helps!
User Guide is the "Low Latency Ethernet 10G MAC
Intel ® FPGA IP User Guide"
Short answer to your question 1 is YES.
I presume you are using Intel Arria 10 FPGA. I think the best way to help you is refer to an existing reference design. The reference design will show you how to configure MAC IP register and also have example on how to generate Ethernet frame packet to MAC IP.