- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
I have task to transmit data from 1 board to another
Each board has FPGA stratix 10M
To do it - I use LVDS SERDES IP in FPGA (TX) and other LVDS SERDES IP in FPGA (RX)
All the pins define as LVDS (including clocks & data)
My problem is : Sometimes pll lock flag doesn't lock
I don't know what is root casue for that - but I sample the clocks by scope
You can find it in the attached pic :
Do I need change the IO standard ?
Do I need change the internal termination ?
BR,
Yishay
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi
Do you know what could be the reason for the unstabilty lock ?
Each reset / PWR on/off or FPGA loading get another lock flag value from the SERDES IP port
Yishay
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
You may want to look into the terminations applied to each of the LVDS pins. Also, you can check on the RREF pins. For more details, please refer the Stratix 10 Pin connection guidelines. https://www.intel.com/content/www/us/en/programmable/documentation/lod1484643014646.html#wsh1484644837897
Regards.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page