LVDS SERDES IP

[ymiler]

Hi 

I use 2 LVDS SERDES IP in my project (TX & RX)

According to your datasheet : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-lvds.pdf   page 39 - There is option to configure external PLL instead of the SERDES IP .

I have 2 questions -

1)Do I need to configure for both (RX & TX IP) external IP or I can configure only for 1 of them-according to page 39 - I must configure in both of them

2)Can I connect clock to the external PLL from global dedicated clock pin but not from dedicated SERDES pin?

Thanks

Yishay

[EngWei_O_Intel]

Hi Yishay

RX and TX shall be independent in selecting internal/external PLL mode. Let me know if you seeing otherwise during compilation.

For SERDES usage, it is always recommended to drive the PLL with dedicated clock.

Thanks.

Eng Wei

[ymiler]

Hi Eng Wei ,

{Eng Wei} RX and TX shall be independent in selecting internal/external PLL mode {YM} = according to your datasheet(page 39) should to be both external PLL :

So , Do I need to configure for both (RX & TX IP) external IP

{Eng Wei}  For SERDES usage, it is always recommended to drive the PLL with dedicated clock.{YM} = Your recommended is for input serdes clock or also for TX serdes  clock ?

Yishay Miller

[EngWei_O_Intel]

Hi Yishay Miller

The diagram is showing the connectivity we need to have for Tx and Rx if they are configured as external PLL mode, as there are no direct connections between Tx and Rx in the diagram. 

Yup, we shall use dedicated clock for both. 

Thanks.

Eng Wei

[EngWei_O_Intel]

Hi Yishay

Since there are no further questions on this, I will transition the thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Eng Wei