LVDS SERDES

[ymiler]

Hi,

I have IP serdes in my FPGA (FPGA A) - 

This SERDES have connection with another FPGA (other board - FPGA B)

According to my project requirements - I should inject(output)  and get(input)  clocks from FPGA A to FPGA B

My question is : Should I place  both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the  input clock ?

Thanks 

Yishay

[AminT_Intel]

Hello,

There is not enough information about your design but as far as I understand you can put both in and out in the dedicated pin. I'd advise you to check on both conditions you mentioned to see which one works.

Thanks

[ymiler]

I drew a little VISIO that describe my design :

My problem is :  Unlock / Lock indication is depend by FPGA loading

I wonder if the root cause is pin location -

My question is : Should I place  both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the  input clock ?

Note : I dont have the option to locate input & output to SERDES pin dedicated clocks ( because board planning) 

Thanks

[AminT_Intel · Accepted solution]

Hello,

Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient.

Thank you.

[AminT_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users

[AminT_Intel]

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