FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

LVDS SERDES

ymiler
Employee
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Hi,

 

I have IP serdes in my FPGA (FPGA A) - 

This SERDES have connection with another FPGA (other board - FPGA B)

According to my project requirements - I should inject(output)  and get(input)  clocks from FPGA A to FPGA B

My question is : Should I place  both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the  input clock ?

 

Thanks 

Yishay

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AminT_Intel
Employee
1,707 Views

Hello,

 

Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient.

 

Thank you.

View solution in original post

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AminT_Intel
Employee
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Hello,

 

There is not enough information about your design but as far as I understand you can put both in and out in the dedicated pin. I'd advise you to check on both conditions you mentioned to see which one works.

 

Thanks

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ymiler
Employee
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I drew a little VISIO that describe my design :

 

ymiler_0-1629014647726.png

My problem is :  Unlock / Lock indication is depend by FPGA loading

I wonder if the root cause is pin location -

My question is : Should I place  both clocks (in & out ) in the dedicated pin clocks or maybe I should do it only for the  input clock ?

Note : I dont have the option to locate input & output to SERDES pin dedicated clocks ( because board planning) 

Thanks

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AminT_Intel
Employee
1,708 Views

Hello,

 

Thanks for the details. Output clock at FPGA A can be placed at any LVDS pair pins and input clock at FPGA B should be sufficient.

 

Thank you.

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AminT_Intel
Employee
1,691 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users

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AminT_Intel
Employee
1,691 Views

Otherwise, the community users will continue to help you on this thread. Thank you.

 

 

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