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LVDS & SerDes MegaCore generation and connections

Altera_Forum
Honored Contributor I
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Dear Sir, 

 

I'm currently using DE4 board to try a Gigabit Ethernet with SGMII design. 

I'm trying to generate LVDS blocks with SerDes for an SGMII application. 

There are three modes, DPA, non-DPA, and soft-CDR described in the  

Stratix IV handbook. For SGMII application, I am supposed to use soft- 

CDR mode. I, however, can't see any selection for the soft-CDR. There  

only one option similar to what we need, shown in the MegaFunction for  

soft-CDR.jpg. Is it the option for SGMII? If it is, why the output clock 

is still 'rx_outclock', but not 'rx_divfwdclk'? 

In addtion, about the connection for the LVDS, for example tx_out_p needs 

to be connected to 'ETH_TX_p0. That is PIN_T30 for the DE4 board. 

How do I connect ETH_TX_n0? Will it be connected automatically? 

Thanks. 

 

 

Peter Chang
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