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LVDS Serdes multi channel bit order (Cyclone 10 GX)

designEngineer
New Contributor I
216 Views

What is the bit order for deserialization of a multi channel LVDS Serdes?

 

From the user guide (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altera_lvds.pdf) figure 3 on page 8 I can see what the bit order is for a single channel. What I can't find is what the bit order looks like if there is more than one channel.

 

For example:

single channel, serdes factor of 8:

input: (7)(6)(5)(4)(3)(2)(1)(0)(a)(b)(c)(d)(e)(f)(g)(h)(A)(B)(C)(D)(E)(F)(G)(H)

output (known from user guide): (7:0)(a:h)(A:H)

 

dual channel, serdes factor of 8:

input: (15:14)(13:12)(11:10)(9:8)(7:6)(5:4)(3:2)(1:0)(a:b)(c:d)(e:f)(g:h)(i:j)(k:l)(m:n)(o:p)(A:B)(C:D)(E:F)(G:H)(I:J)(K:L)(M:N)(O:P)

output (unknown): (?:?)(?:?)(?:?)

 

What does the output look like and where can this information be found?

 

Thank you for your help!

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1 Reply
ShafiqY_Intel
Employee
174 Views

Hi designEngineer,

 

Serializer = Parallel data to Serial data, normally we call this as TX. Meaning parallel data from core become serial data at output pin.


Deserializer = Serial data to parallel and we call this as RX. Serial data to pin and pass thru the Deserializer block to parallel data to core.

 

 

For dual channel, SERDES factor of 8:

ShafiqY_Intel_0-1596682448450.png

Let's assuming you have two channels as above and the pattern is repeated pattern for respective channel (rx_in & rx_in2). In which mean rx_in always 12345678 12345678 12345678……  and rx_in2 alaways abcdefgh abcdefgh abcdefgh...

When you create a design with dual channel in single IP, the representation block will be something as above and each parallel rx_out[15:0] are {12345678 abcdefgh} {12345678 abcdefgh} {12345678 abcdefgh} {12345678 abcdefgh}

 

I hope it is clear now.

 

Regards,

Matt

 

 

 

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