Hello,I am trying to implement a LVDS to RGB converter in the DE1 board. I am using the LVDS and PLL IP Megafunction. I used as a template the "Design Example 2: Cyclone II ALTLVDS Using External PLL Option" from the ALTLVDS Megafunction User Guide. I changed the FPGA used because it's not the exact same one as in the DE1 board. Then when I am assigning the pins to the expansion header of the DE1 board (I also precise in the "I/O Standard": LVDS), Quartus Fitter gives me the following error: "Error: Can't place PLL "lvds_pll:inst2|altpll:altpll_component|pll" -- I/O pin "ref_clock" (port type INCLK of the PLL) is assigned to a location which is not connected to port type INCLK of any PLL on the device" Can somebody explain to me what this error means and how I can solve it? Thank you in advance, Meach
Hello Ton,Yes I am using one I/O pin from the expansion header because I thought that I need to get somehow the LVDS clock. If I want the LVDS data to be synchronised, how can it be if I don't have its clock in input? Meach
Aditionally, you can't use LVDS with the DE1.The GPIO pins are connected to a bank powered at 3.3V VCCIO. For LVDS, they'd have to be connected to a back with 2.5V VCCIO and have the proper external resistors. Among the examples and documentation of the DE1 board, you should have a mock up project that contains just an empty top level and all the correct pin assignments. I suggest you take it as base for any project you do on the DE1.
Oh great!There is no possibilities to use it anyway with the DE1? For the pin assignment I prefer doing it myself for any project. I prefer to check them anyway every time and so far I do not need to assign every time all the pin of the board. Meach
So like rbugalho wrote: no LVDS for DE1. Too bad.But if you ever gonna design your own board, make sure your LVDS-clocks are connected to a pinpair labeled "LVDSCLK" in http://www.altera.com/literature/dp/cyclone2/ep2c20_ep2c15a_ep2c20a.pdf. And make sure the external termination is right (I used 100 Ohm with success). Good luck, Ton
For now I am only interested in development board but if I will design my own one later, I will keep that in mind.Also this is a bit off topic but basically if I want to use the LVDS protocol with a development board, I have to make sure that the board has adjustable Input Signal Levels, right? rbugalho said that it should be connected to 2.5 VCCIO. But I read that the maximum input voltage of LVDS is 2.4 V. So for example with 1.8 VCCIO, will it work? Thank you Meach
To use LVDS with a development board, the board needs to have a LVDS interface.IIRC, the Cyclone III starter kit has. VCCIO is the voltage that powers the I/O elements. The maximum LVDS signal voltage is 2.4V but the FPGA I/O elements must be powered with 2.5V for LVDS. Trying to use LVDS with 1.8V VCCIO is not document anywhere, AFAIK, and it will problably not work.
ok thank you rbugalho, that's exactly what I wanted to hear!I made some research and instead of looking for another development kit I think I will go for a Quad Link LVDS Interface HSMC Daughtercard + GPIO-HSMC Card and the DE1. Meach