LVDS in Stratix iv

[Altera_Forum]

Hi, 

 I'm working on a project with a pair of high speed LVDS ports. The FPGA board that I'm using is DE4 which is using a stratix IV EP4SGX530 as the FPGA. How can I check if the LVDS is working? The LVDS that I am using is made by the Quartus IPcatalog. It is an LVDS with soft DPA SerDes for SGMII. It is runing in a frequency of 125Mhz for the parallel and 1.25Ghz for the serial port. I can the the transmission locked at the tx_lvds. I however can see  anything on the PHY after the LVDS. Can I slow down the speed and connect the LVDS output back into the FPGA to check if it is  working?  Thanks,  Peter Chang

[Altera_Forum]

--- Quote Start ---  Hi,  I'm working on a project with a pair of high speed LVDS ports. The FPGA board that I'm using is DE4 which is using a stratix IV EP4SGX530 as the FPGA. How can I check if the LVDS is working? The LVDS that I am using is made by the Quartus IPcatalog. It is an LVDS with soft DPA SerDes for SGMII. It is runing in a frequency of 125Mhz for the parallel and 1.25Ghz for the serial port. I can the the transmission locked at the tx_lvds. I however can see  anything on the PHY after the LVDS. Can I slow down the speed and connect the LVDS output back into the FPGA to check if it is  working?  Thanks,  Peter Chang  --- Quote End ---      Hi,  Some experience and clarification, after hard working on the LVDS, are able to share with all you need. In the last question, I've asked about the LVDS in my last mail. There are some typos inside. Let me correct the whole post again below please. And some questions have answers that will be shown after.   I'm working on a project with a pair of high speed LVDS ports. The FPGA board that I'm using is DE4, which is using a stratix IV EP4SGX530 FPGA. How can I check if the LVDS is working?  Answer: I can use the HSMA loopback to check LVDS.   The LVDS that I am using is made by the Quartus IPcatalog. It is an LVDS in the mode of soft CDR for SGMII. It is runing in a frequency of 125Mhz for the parallel and 1.25Ghz for the serial port. I can see the the transmission locked at the tx_lvds. I however can not see anything on the PHY after the LVDS. Can I slow down the speed and connect the LVDS output back into the FPGA to check if it is  working?  Answer : Yes, through HSMA loopback.    Peter Chang

[Altera_Forum]

Hi, 

 The problem doesn't not totally solved yet. Even the LVDS loopback has been done. The LVDS for SGMII to PHY isn't as expected working well. I don't know why? Are there any experts who can solve the problem? PHY is now link up. But there are no TX LED and RX LED lighted on. It seem having no data tranmitting on PHY. A little confused.  Thanks,  Peter Chang