Loosing data because Rapidio is not ready during large data transfers

[Sunnyaloc]

I'm want to know if I have to follow any guidlines to get maximum bandwidth out of Rapidio

Rapidio configuration I use is as below.

Right now I use Rapidioii with 1250 Mbaud and 125Mhz reference frequency. 

Not using burst mode as I have to transmit 32 bit data per 300ns.  Which is far less than the maximum bandwidth.

The problem is that the Rapidio is not "ready" sometimes making the internal FIFO full and inturn loosing the data. I increased the FIFO depth from 4 DWords to 2048 Dwords. Still I see this issue when I transmit large amounts of data. 

Is there a way to improve Rapidio's performance to make it ready most of the time?

[paveetirrasrie_Intel]

Hi Adithya,

May I know which device are working with? Meanwhile, I've attached UG for RapidIO II where it describe the possible suggestion to transmit larger data.

https://www.intel.com/content/www/us/en/docs/programmable/683444/20-3/enable-16-bit-device-id-width.html

Regards,

Pavee

[Sunnyaloc]

Hi Pavee, Thanks for your reply. I'm using Rapidioii in Arria10 and ArriaV. I see the same issue in both the FPGAs. 

First the IP is going out of ready and then internal buffers are going full. This results in port_error

I tried what you suggested by enabling the 16bit device ID on Arria10. This didn't resolve the issue. I see the problem as mentioned above.

[paveetirrasrie_Intel]

Hi Aditya,

Good day to you.

Since similar case has been open in new IPS thread, I shall set the case to close. Further support will be provided through IPS.

Regards,

Pavee