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Low Latency 100G with RS-FEC fails placement on Stratix 10 H-tile




We're attempting to route a 100G interface with RS-FEC. When we configure the IP without RS-FEC, it routes, but when we enable RS-FEC, it consistently fails to successfully place the design. When we disable RS-FEC, the design routes.


We suspect the problem relates to our SDC file, but we're not sure how to modify it. The current design only includes the 100G interface, with minimal logic to support ethernet control packets (and which has been validated to work over a 40G interface).


Are there additional constraints we should be looking at? 


I noticed that the user guide says that sometimes we may have to conduct floor planning - is that often the case?





# Specify the number of 40G interfaces:
set x100g_count 4

# Time Information

set added_uncertainty_312mhz 0.48ns
set added_uncertainty_390mhz 0.424ns

# Create Clock

# 100G clocks

for { set i 0 } { $i < $x100g_count } { incr i } {
    set cg_ref_clk [get_ports cg_ref[$i] ]
    create_clock -name cg_ref[$i] -period 1.551515152 $cg_ref_clk
    # set cg_ref_clk to 0, in case if one element in the loop failed to assign correct value
    # to cg_ref_clk, the next value wouldn't have a duplicate clock
    set cg_ref_clk 0

# Get clock info for 100G RT, TX and IOPLL clocks:
#set IOPLL_LOCKCLK   [list]
set RX_CORECLK      [list]
set TX_CORECLK      [list]
set RX_RS_CORE_CLK  [list]
set RX_RS_CORE_NCK  [list]
set TX_RS_CORE_CLK  [list]
set REF_CLK         [list]

set SYSTEM_TIME_CLK [get_clocks {fpga_ref_pll|iopll_0_outclk0}]
# This is the clock from TRx125MCalClk pin which is 100 MHz.
set STATUS_CLK      [get_clocks {mgmt_clk_pll|iopll_0_outclk0}]

for { set i 0 } { $i < $x100g_count } { incr i } {
    set THIS_RX_RS_CORE_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_outclk0]
    set THIS_RX_RS_CORE_NCK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_n_cnt_clk]
    set THIS_TX_RS_CORE_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|TXPLL_IN.TXFPLL_INST.tx_pll_gen.fectxpll|clkdiv_output_div1]
    set THIS_RX_CORECLK     [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|rx_clkout2|ch1]
    set THIS_TX_CORECLK     [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|tx_clkout2|ch1]
    set THIS_REF_CLK        [get_clocks cg_ref[$i]]

    lappend RX_RS_CORE_CLK [get_clock_info -name [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_outclk0]]
    lappend RX_RS_CORE_NCK [get_clock_info -name [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|RXIOPLL_INST.fecrxpll|alt_e100s10ex_iopll_rx_n_cnt_clk]]
    lappend TX_RS_CORE_CLK [get_clock_info -name [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|WITH_FEC.fecpll|TXPLL_IN.TXFPLL_INST.tx_pll_gen.fectxpll|clkdiv_output_div1]]
    lappend RX_CORECLK    [get_clock_info -name [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|rx_clkout2|ch1]]
    lappend TX_CORECLK    [get_clock_info -name [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|tx_clkout2|ch1]]
    lappend REF_CLK       [get_clock_info -name [get_clocks cg_ref[$i]]]

    set_clock_groups -exclusive -group $THIS_TX_CORECLK -group $THIS_RX_CORECLK -group $THIS_TX_RS_CORE_CLK -group $THIS_RX_RS_CORE_CLK -group $THIS_RX_RS_CORE_NCK -group $TRS_DIVIDED_OSC_CLK -group $STATUS_CLK -group $REF_CLK


if {![is_post_route]} {
    set_clock_uncertainty $added_uncertainty_312mhz -add -from $RX_RS_CORE_CLK -to $RX_RS_CORE_CLK -setup
    set_clock_uncertainty $added_uncertainty_312mhz -add -from $TX_RS_CORE_CLK -to $TX_RS_CORE_CLK -setup
    set_clock_uncertainty $added_uncertainty_312mhz -add -from $RX_RS_CORE_NCK -to $RX_RS_CORE_NCK -setup
    set_clock_uncertainty $added_uncertainty_390mhz -add -from $RX_CORECLK -to $RX_CORECLK -setup
    set_clock_uncertainty $added_uncertainty_390mhz -add -from $TX_CORECLK -to $TX_CORECLK -setup

} else {
    # everywhere else

set_clock_groups -exclusive -group $TX_CORECLK -group $RX_CORECLK -group $TX_RS_CORE_CLK -group $RX_RS_CORE_CLK -group $RX_RS_CORE_NCK -group $TRS_DIVIDED_OSC_CLK -group $STATUS_CLK -group $REF_CLK

set_clock_groups -exclusive -group [lindex $TX_CORECLK     0] -group [lindex $TX_CORECLK     1] -group [lindex $TX_CORECLK     2] -group [lindex $TX_CORECLK     3]
set_clock_groups -exclusive -group [lindex $RX_CORECLK     0] -group [lindex $RX_CORECLK     1] -group [lindex $RX_CORECLK     2] -group [lindex $RX_CORECLK     3]
set_clock_groups -exclusive -group [lindex $TX_RS_CORE_CLK 0] -group [lindex $TX_RS_CORE_CLK 1] -group [lindex $TX_RS_CORE_CLK 2] -group [lindex $TX_RS_CORE_CLK 3]
set_clock_groups -exclusive -group [lindex $RX_RS_CORE_CLK 0] -group [lindex $RX_RS_CORE_CLK 1] -group [lindex $RX_RS_CORE_CLK 2] -group [lindex $RX_RS_CORE_CLK 3]
set_clock_groups -exclusive -group [lindex $RX_RS_CORE_NCK 0] -group [lindex $RX_RS_CORE_NCK 1] -group [lindex $RX_RS_CORE_NCK 2] -group [lindex $RX_RS_CORE_NCK 3]

# From "AV SoC Golden Hardware Reference Design"
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tdi]
set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_tms]
#set_input_delay -clock altera_reserved_tck -clock_fall 3 [get_ports altera_reserved_ntrst]

# Set Output Delay

set_output_delay -clock altera_reserved_tck 3 [get_ports altera_reserved_tdo]

# Set Clock Groups
#set_clock_groups -asynchronous -group $RX_CORECLK \
#                               -group $TX_CORECLK \
#                               -group $STATUS_CLK \
#                               -group $SYSTEM_TIME_CLK

#set_clock_groups -asynchronous -group $IOPLL_LOCKCLK \
#                               -group $STATUS_CLK

# set false path from PMA fifo flags' clock to clk_status (ex_100g_inst|ex_100g_inst|alt_s100|csr|eio_flags_csr[*])
for { set i 0 } { $i < $x100g_count } { incr i } {
    for {set chNum 0} {$chNum < 4} {incr chNum} {
        set RX_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|rx_pcs_x2_clk|ch$chNum]
        set TX_CLK [get_clocks gen_XG[$i].xg_wrapper|GEN_100G.av_top|alt_e100s10_0|xcvr|tx_pcs_x2_clk|ch$chNum]
        set_clock_groups -exclusive -group $RX_CLK -group $STATUS_CLK -group $TRS_DIVIDED_OSC_CLK
        set_clock_groups -exclusive -group $TX_CLK -group $STATUS_CLK -group $TRS_DIVIDED_OSC_CLK

set_clock_groups -exclusive -group $RX_CORECLK -group [get_clocks {mgmt_clk_pll|iopll_0_refclk}]
set_clock_groups -exclusive -group $TX_CORECLK -group [get_clocks {mgmt_clk_pll|iopll_0_refclk}]

set_clock_groups -exclusive -group $RX_CORECLK -group [get_clocks "mgmt_clk_pll|iopll_0_refclk"]
set_clock_groups -exclusive -group $TX_CORECLK -group [get_clocks "mgmt_clk_pll|iopll_0_refclk"]

set_clock_groups -exclusive -group $STATUS_CLK -group [get_clocks {mgmt_clk_pll|iopll_0_refclk}]
set_clock_groups -exclusive -group [get_clocks {mgmt_clk_pll|iopll_0_refclk}] -group $STATUS_CLK

# Set False Path

set_false_path -to o_40GA_LED[*]
set_false_path -to o_40GB_LED[*]



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