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Low Latency Ethernet 10G MAC (QSE): Receive pktstatus error 0x20 (bit 5)

Altera_Forum
Honored Contributor II
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Hi, 

 

I'm currently debugging issues with the QSE 10G IP core embedded into an 

FPGA (Arria10) connected via PCIe to the system CPU (PC). 

Sometimes the RX mSGDMA reports this error: 

 

RCV pktstatus 00000020 pktlength 00000558 

... 

 

My current best guess about the pktstatus read from the mSGDMA controller 

(status from the response FIFO), is that it represents rx_status/error from the 

MAC (MAC manual page 90): 

avalon_st_rxstatus_error[] 

Out 7 When set to 1, the respective bit indicates thefollowing error type in the RX frame. 

• Bit 0: Undersized frame. 

• Bit 1: Oversized frame. 

• Bit 2: Payload length error. 

• Bit 3: CRC error. 

• Bit 4: Unused. 

• Bit 5: Unused. 

• Bit 6: PHY error. 

The IP core presents the error status on this bus in the same clock cycle it asserts 

the avalon_st_rxstatus_valid signal. The error status is invalid when an overflow 

occurs. 

 

Is this assumption correct? And if yes, 0x20 means bit 5 and this is "Unused" in the 

table above. So what could this error mean? 

 

Thanks, 

Stefan 

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