FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6228 Discussions

Low-latency 100G Ethernet l8_tx_ready toggling

New Contributor I


I am using the low-latency 100G Ethernet IP (with RS-FEC enabled). I needed to use signal tap to debug something, and I observed the behavior of the Avalon stream interface and I noticed that l8_tx_ready signal is toggling :

-high for 11 clock cycles

-low for 11 clock cycles 

(Clock frequency is 390.625MHz).

I thought that this signal was supposed to stay high when I don't send any packets. 

Do you know what could cause this ? It impacts my design as it divides the bandwidth by a factor of 2.



0 Kudos
0 Replies