I am finding a way of verifying the Quartus dual image IP on my board. The FPAG on the board is 10M16DAU324.
Firstly, I had tested the CONFIG_SEL pin which did change the boot image so the IP seemed good.
And then I found a document which listed that CRC error and watchdog timeout would cause the remote system upgrade feature to load another application configuration image.
However, the FPGA did not reconfigure after I injected an soft error by changing the 32-bit CRC option register.
Does anyone know how to verify it?
Yes it will. May i know how do you inject the soft error? Are you using the JAM file to inject as shown in link below?
I used Quartus JTAG chain debugger to access CHANGE_EDREG JTAG Instruction.
The CRC_ERROR pin did go high when I changed the CRC storage register.
It seems the JAM file would do the same thing.
And I am curious if dual IP core support re-configuration in user mode, since these methods would only inject soft error in user mode.