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Altera_Forum
Honored Contributor I
1,275 Views

MII TSE Deisgn

Hello, 

 

i have a few problems with my TSE design. I want to use MII between the MAC and PHY (DP83848C), which is supported by the IP-Core. 

I have successfully set up a communication over RGMII on the DE2-115 board from Terasic with the help of a guide from Altera, "Using Triple-Speed Ethernet on DE2-115 Boards". Now I want to port the system to a DE0-Nano with an external PHY.  

I choose GMII/MII in the TSE configuration, I use my code from the DE2-115 board with a few changes for 100MBit mode, the LEDs on the external board are blinking, but I cant receive anything. I think there is something wrong with my PHY initialization, but I don't know what. Is someone here who has a full working setup with the DP83848C over MII? I'm working with Quartus 16.1 and don't use Iniche or something, I want to use the plain C interface like in de guideline from Altera. 

If there is something more you want to know, don't be afraid to ask. 

 

Hope for a reply, 

Donni
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3 Replies
Altera_Forum
Honored Contributor I
23 Views

Hi Donni, 

 

we use the TSE with a Marvell 88E1111 Phy. When changing from GMII/RGMII to MII I use a clock mux for the tx_clk. In case of 100MBit the Phy provides a 25 MHz clock. In 1000MBit mode the tx_clk (125 MHz) is generated in the FPGA. 

May be you have to consider this for the Phy you using? 

 

regards 

Jens
Altera_Forum
Honored Contributor I
23 Views

Hello Jens, 

 

thanks for your reply. I am not sure if I have a clock problem or an initialization problem (in C Code). I generate a 25 MHz clock with the FPGA for the PHY and I don't need a 125 MHz clock because I only use a 100Mbit PHY on the DE0/Nano. Are you using the Iniche TCP Stack or are you initialize the TSE by yourself? 

 

Nobody here, who hast a working setup with a DP83848C PHY? 

 

regards, 

Donni
Altera_Forum
Honored Contributor I
23 Views

Ah, o.k. Yes I'm using Iniche Stack.

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