MSGDMA Prefetcher Initialization Error

[aln]

Hello,

We have a custom hardware solution using Cyclone IV. This is an old design using Quartus 12.0.

We're planning to transition to an Arria 10 with a SoC and therefore we are preparing our design and software to be compatible with Quartus 20.1.

First we could not get the SGDMA to work properly and after doing some investigation it seems like SGMDA isn't supported any more. 

We exchanged the SGDMA with the MSGDMA, but now we're stuck in the alt_msgdma_init() routine where the reset bit never seems to clear.

We're unsure on what we've done wrong. Any help is appreciated.

void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq)
{
    extern alt_llist alt_msgdma_list;
    alt_u32 temporary_control;
    int error;

    if (dev->prefetcher_enable)
    {
        /* start prefetcher reset sequence */
        IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base, 
                ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
        /* wait until hw clears the bit */    
   
        // Locks inside of this while loop while waiting until HW clears the reset bit       
        while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
            IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)));
        ...

[EricMunYew_C_Intel]

You can refer to below for reference:

https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

[DeanK77]

How is this answering his question in a reasonable manner? How about a reference design that does not need quartus pro. How about just converting all the older devkit files to support msgdma modules and in something greater than quartus 14 or 15 instead of leaving developers hanging with old sgdma designs that ALWAYS have issues like this with the msgdma modules when translating from sgdma. How about not obsoleting something in the BSP generator until you have new reference material and dev kit reference designs that "just work" with the new msgdma modules. Come on, we expect more that this!

[dgal0215]

Did you find a workaround for this?  I've put many hours into trying to resolve the same issue, without any luck

Regards,

Derek

[DeanK77]

Derek,

Yes but only with a new reference design starting point because the anything starting pre 17.x is doomed due to the SGDMAS-> MSGDMA conversion requiring significant driver changes too. So start with the below link as a reference. Its in 18.1 already so no need to migrate the SGDMAs as it already uses the MSGDMAs. I was able to get this version to work and then use as the launching point for my modifications. This should get you going!

https://fpgacloud.intel.com/devstore/platform/18.1.0/Standard/nios-ii-simple-socket-server-ethernet-example-for-deca/

[dgal0215]

DeanK77 - really appreciate the assistance and quick response on this!!  I'll download this example and start integrating!