Hello,
We have a custom hardware solution using Cyclone IV. This is an old design using Quartus 12.0.
We're planning to transition to an Arria 10 with a SoC and therefore we are preparing our design and software to be compatible with Quartus 20.1.
First we could not get the SGDMA to work properly and after doing some investigation it seems like SGMDA isn't supported any more.
We exchanged the SGDMA with the MSGDMA, but now we're stuck in the alt_msgdma_init() routine where the reset bit never seems to clear.
We're unsure on what we've done wrong. Any help is appreciated.
void alt_msgdma_init (alt_msgdma_dev *dev, alt_u32 ic_id, alt_u32 irq)
{
extern alt_llist alt_msgdma_list;
alt_u32 temporary_control;
int error;
if (dev->prefetcher_enable)
{
/* start prefetcher reset sequence */
IOWR_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base,
ALT_MSGDMA_PREFETCHER_CTRL_RESET_SET_MASK);
/* wait until hw clears the bit */
// Locks inside of this while loop while waiting until HW clears the reset bit
while(ALT_MSGDMA_PREFETCHER_CTRL_RESET_GET(
IORD_ALT_MSGDMA_PREFETCHER_CONTROL(dev->prefetcher_base)));
...
