I have been attempting to use the Chip ID IP core with Max10. What I'm finding is a disagreement in the internal Altera/Intel documentation. First of all, the Chip ID Intel FPGA IP Cores User Guide says that Max 10 is not included in the devices that work with the IP core.
Second, in the Max10 configuration guide, it says that it does. Finally, after messing with the design, I am able to get it to synthesize. Why doesn't the Chip ID Intel FPGA IP Cores User Guide include Max 10 ????
Max 10 device have been included into Unique Chip ID User Guide.
Thank you for your feedback.
Considering that I have been using Unique Chip ID for several months now in Max10, glad to see that it finally made it to the documentation.