Hi, I am using trying use SGDMA to transfer video from streaming to memory in a windowed frame.
I built system and inferred SGDMA into QSYS, tryid two addresses , first 0x110a300 then 0x110A200, at both addresses register seems not working except register 1, forever rerturn zero and don't accept be written, if modified by debugger return again zero ( 1 for reg 1) and write error message. Target board is a BEMicro MAX 10 whit an LCD panel and a video sampler logic, LCD is working fine also NIOS but I found no way to start DMA transfer from SGDMA. To try fight where problem can arise I manually added a port to NIOS module interface then I exported the signals from dual clock module and SGDMA to exetrnal pin attaching simple LA. Chip select pulses are ok, Valid to SGDMA is High but forever REady from DMA is stuck at 0 nor DMA get initialized and status register never come to life.. I have no idea of what can be worst, I am grateful if someone can help me point out what can be wrong, I am not so expert on Qsys and some module are custom but seems have nothing to do with problem and tested alone perform fine. Platform: Quartud II web edition 15,1 Linux 64bit Mint version 17.2 Target BEMicro MAX 10 There is no space for signal tap LA but I can export all signals from Avalon interface and hook up to a real LA or port to a larger FPGA if necessary. CRT Genlocker ignore backpressure, module just stream out assembled pixel gathered from source. Best regards