Can anyone confirm that the Megawizard single clock fifo (scfifo) does not work correctly in the usedw, almost_full, and full outputs? When I try to use this form of the fifo (with a single clock for input and output) those signals are just not right.
I'm using a Cyclone III FPGA (but it should not matter which hardware it uses). I'm looking at the ModelSim simulator results.
I have set up a simple fifo of 8 bit words and 8 words long. Then I start clocking in bytes. For the first 2 bytes the signals seem OK, the usedw begins to count up and after the latency the empty flag goes false. But as I clock in more bytes the usedw count never increases past 2 and the almost_full and full flags never go true. I am not reading any bytes out, just trying to load them into the fifo for now.
If I try the same thing with the dual clock form of the fifo it works perfectly.
Anyone noticed this trouble?
