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JonyC
Beginner
92 Views

Memory port width vs initialization content

Hello,

I use embedded ROM in my Cyclone V FPGA (5CEFA4F23C6) and I am confused by output of the ROM with regards to initialization content (Intel HEX file).

ROM has 2-bit wide output bus and 13312 words (2-bit words), single clock with rden and registered output.

JonyC_2-1611755452775.png

When I simulate the design (where I read the content) it looks like the address corespond to the bytes in the memory - not to the 2-bit words. So the memory expose only two least significant bites of the bytes in the memory - see image below.

Memory initialization content:

JonyC_0-1611754979939.png

Output of the memory - simulation:

JonyC_1-1611755267976.png

I assumed that next 2 BITS wil be exposed to the output when I incement the address.

Is it correct behaviour of the memory with this configuration?

Thanks for the responses

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1 Reply
SyafieqS_Intel
Moderator
28 Views

Hi Jonas,


Any update on the issue?


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