I use embedded ROM in my Cyclone V FPGA (5CEFA4F23C6) and I am confused by output of the ROM with regards to initialization content (Intel HEX file).
ROM has 2-bit wide output bus and 13312 words (2-bit words), single clock with rden and registered output.
When I simulate the design (where I read the content) it looks like the address corespond to the bytes in the memory - not to the 2-bit words. So the memory expose only two least significant bites of the bytes in the memory - see image below.
Memory initialization content:
Output of the memory - simulation:
I assumed that next 2 BITS wil be exposed to the output when I incement the address.
Is it correct behaviour of the memory with this configuration?