FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP

ModelBus - RegField

Honored Contributor II

Good afternoon, 


I have a nice DSP Builder model integrated with a NIOS II processor. Everything works well. 


I'm trying to use the RegField in the DSP Builder Advanced Blocks/ModelBus library. After reading the 'help' and searching online I'm still a bit confused: 


1- The help text mentions for most ModelBus blocks that "... accessible in the model and via the Processor Interface". Am I right to assume that this "Processor Interface" allows me to modify my parameters stored in the RegField block at run time with the NIOS II core ? 

2- If yes... Where do you configure or access this wonderful "Processor Interface" ?  

3- Does it need to be configured with QSys or is there a special macro that can be used in code ? 


... Or is the Processor Interface a tool that I missed somewhere ? 


Thanks in advanced for any kind of help. 


Carl 'BigK'
0 Kudos
2 Replies
Honored Contributor II

DSP Builder creates a hw.tcl file which you can use to import your design into Qsys. If you have ModelBus blocks (or FIRs/NCOs with read/writable coefficients/increments), it will export a Avalon MM slave. If you write to the address you set in the Address field (possible misnamed Name in the parameter window) then you will modify that register.

Honored Contributor II

I added the RegField block AFTER my model was loaded in QSys. Having not refreshed my IP list the Avalon bus was not visible. I created a new model from scratch and fare enough the Avalon bus is now visible and can be connected to the master. 


Thank you for your time!