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Dear all, has anyone encountered the issue described below?
I generate a floating-point number division IP using Quartus 18. Then I used Altera-Modelsim to simulate the results. These are fine and working. Then, I moved all the files to another computer and also with Quartus 18 installed. Then, I run the simulation on this other computer. This time Altera-Modelsim on the second computer returns the error message below
# ** Error: (vsim-3389) C:/Users/Testproject/fp_div14.v(1341): Port 'sclr' not found in the connected module (7th connection).
Does anyone know how to fix this issue or point me to some references?
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Without seeing any code or the testbench, there's no way to really help here.
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Could you help to share the design .qar file and testbench, to take a further look?
Best Regards,
Richard Tan
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Hi,
Do you able to provide the design file and testbench?
Regards,
Richard Tan
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
Thank you.
Best Regards,
Richard Tan
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.

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