I am looking to implement PCIe hard IP to transfer data from an FPGA device to a host in the future, I have done a similar thing previously using Xilinx IP components that allow use of many separate queues in the host software.
I was looking at the Multi Channel DMA IP for the Stratix 10 device linked here https://www.intel.com/content/www/us/en/programmable/documentation/xzr1589413426034.html
Even though it says that there is one DMA channel "per port" in the feature list, Table 11 for the QCSR register seems to indicate there will be support for multiple channels per port in the future. I'd say this is confirmed as the software describes up to 2048 H2D and D2H queues and there is an associated signal at the end of table 33/34 with the description 'To support multi-Channel per port. For future purpose.'
So my question is, when can I expect these features to properly become part of this IP and is there any further information on its operation?
Thanks in advance,
Yes, seem like the IP is designed feasible to enable the multi-channel for AVST. However, there is no plan to enable it in any future version yet. I guess the reason is there is no marketing request for this feature. If you want to make this happen in future for usage, please contact sales representative in your region.