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Honored Contributor I

Multi channel TSE with GBX (Arria II GX)

In one of our future boards, we+re going to use an Arria II GX FPGA, which will have 5 Ethernet connection using either SGMII or 1000-X. 

I'm current ly working with an Evalboard using an SMA connector daughter card, so we can connect the design to our backplane. 

Since I need to group the connections in GBX group I created a MegaFunction TSE with four channel using GBX. And our logic we+re using in other design, conatining a PING module. 

If I can connect to Channel 0 every works fine. I get link and can ping the FPGA. If I connect to another channel, I get link, but now activity. 


I tried to connect a GBX_reconfig block, but the design doesn't compile. And end up with a message that atom is already occupied. 

Also if I don't instantiated a GBX reconfig module, I'm getting a critical warning, that CMU is not connected correctly. 


I checked all documentation I found, I'm not getting further. Has anybody tried to generate a TSE with multichannel and GBX ?
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3 Replies
Honored Contributor I

My bad: Forgot to write to the register of the other channels. Works now.

Honored Contributor I

Hello Videoman, 


I am trying to use a Multiport TSE MAC using the Altera's ST multi-channel FIFO. But any port of TSE MAC that should be connected to an external FIFO has an different associated clock. Because of that, I am not being able to connect all the ports from TSE to a Multiplexer to be latter connected on the multi-channel FIFO as suggested in the documentation. When I try to use the Altera's ST Multiplexer I get the following error messages: 


"Error: System.tse: tse.receive_0 and multiplexer_0.in0 must be on the same clock domain, since they're connected" 

"Error: System.tse: tse.receive_1 and multiplexer_0.in1 must be on the same clock domain, since they're connected" 

... and so on for all the ports I try to fit 



So, may I ask, how did u do with the external TSE FIFOs of your multiport TSE design? 


Thank you
Honored Contributor I

We use the RX and TX clocks to find dual clock FIFOs which go than to the target clock domain.