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S10PCIE
Beginner
929 Views

Multiple BARs on Stratix 10 PCIE IP

Do you have any error report when you use multiple BARs of "Stratix 10 Avalon-MM Interface for PCI Express Solutions" of Quartus prime pro 17.1 ? We try to use BAR0 and BAR2 on "Stratix 10 GX FPGA Development Kit" (ES version, DK-DEV-1SGX-L-0ES), which has a 1SG280LU3F50E3VGS1 device. BAR0 has no problem, but we cannot write BAR2 (no write enable signal from Hard-IP).

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Nathan_R_Intel
Employee
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There is no error reported when using multiple BARs on Stratix 10 AVMM for Quartus Prime Pro 17.1. All known issues are captured in the following page: https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/kdb-fi... As you mentioned you are able to write to BAR0 successfully. Hence, I am suspecting either you are not accessing the BAR address correctly or using burst mode. If burst mode is enabled; then you will need to "Enable burst capability for RX Avalon-MM BAR<n> Master ports." Please advice if you are performing the above.
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