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Altera_Forum
Honored Contributor I
1,518 Views

Multiple DSP Builder designs with conflicting VHDL

We have several designers on our team, each creating their piece in DSP Builder. We then pull all of these blocks together into the FPGA. 

 

The problem is that these various DSP Builder designs use identical filenames within their project for similar functions. For example, if 2 designs use a 1-cycle delay block, then that delay block is generated in both DSP Builder designs, and when we pull in each project, 2 of these .vhd files are imported. 

 

Naturally, when Quartus II compiles 2 of these files, both with the same filename and entity name, an error occurs (Quartus doesn't know which entity to use). It has gotten to the point that there are just too many duplicate files (hundreds) to hand edit and/or delete. Has anybody else encountered this situation, and if so, how did you solve it? 

 

Thanks,
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11 Replies
Altera_Forum
Honored Contributor I
33 Views

Are you including the mdl file directly into your top-level Quartus II project or are you including the HDL output of DSP Builder?

Altera_Forum
Honored Contributor I
33 Views

We are including the HDL output (via directly calling them or via the generated .qip files). We are not including mdl files.

Altera_Forum
Honored Contributor I
33 Views

Would it be possible to include the MDL files directly rather than the HDL? If you did this, then quartus would likely generate all the HDL into the same place in the db directory and then you wouldn't get the clashes.

Altera_Forum
Honored Contributor I
33 Views

I can give that a try. 

 

I don't see a .mdl file in the subsystem's directories, but there is a .mdlxml. Is that the one you mean?
Altera_Forum
Honored Contributor I
33 Views

The mdlxml file is generated from the mdl file. I believe you can include that in your project in lieu of the MDL file. (If you included the MDL file with no MDLXML file it would probably attempt to regenerate the MDLXML file using MATLAB which is often undesirable).

Altera_Forum
Honored Contributor I
33 Views

another work around is creating a QXP for each of the DSP Builder projects and integrating them into a single top level project. dabuk's solution of using the mdl instead sounds good too.

Altera_Forum
Honored Contributor I
33 Views

I have same problem with multiple DSP Builder projects. I'll have a try according to your solutions. Thanks in advance~

Altera_Forum
Honored Contributor I
33 Views

Altera_Forum
Honored Contributor I
33 Views

I solved the problem by generating all the VHDL files into one directory, so that same file will be coverd. And all the qip files point to unique file without conflict. 

When I have free time, I will try qxp solution.  

Thank you~
Altera_Forum
Honored Contributor I
33 Views

that's an interesting idea!

Altera_Forum
Honored Contributor I
33 Views

And it works - ok, source files generated from DSP-Builder that have the same filename/entity are being overwritten. But they have identical content (at least in my case) - so all design information exported from Simulink/DSP-Builder is still available top level design (see thread# 154841). 

It's also possible to keep separate HDL folders for each module and just remove duplicate entries from the other .qip-file(s). 

Thanks souvir for this great tip. :)