Hello,my design strictly needs to be a single processor system. In my design, I need to interface 3 Ethernet ports using a single Nios processor. For this purpose, I have added 3 TSE MAC IPs in my Qsys design. I also have 3 descriptor memories for each of the 3 TSE MACs, 3 SGDMA IPs for the RX and TX(total 6) of the TSE MAC. Apart from this, I also have DDR3 controller, flash controller and other peripherals like UART, system timer etc. I need to interface these 3 ethernet ports in Nios. For this purpose, I have made the sample project on lines of Altera's Simple Socket Server example. In my example, after making necessary changes, I am able to autoneg with all the 3 MACs. However, I am unable to ping from PC on any of the 3 static IPs that I assign in my code. My first guess is I havent designed my qsys system correctly; to be more specific, my architecture of TSE MAC and SGDMA is not properly structured. Altera's sample ethernet example suggests the use of Avalon MM Pipeline bridge and making a subsystem for SGDMA and TSE MAC IPs and then connect them to Nios processor via this pipeline bridge. Can someone please tell if this itself might be the cause of ping not coming(if yes, please can you give any reference design links or any help in my existing design) or is there any other issue? please help. I have tried pinging with windows firewall disabled but still no success. Have a look at my design. I am working on Stratix V 5SGXMA7N2F45I3. Thanks in advance.
To isolate whether this is software driver, IP, or system design, you need to capture the signal tap at the TSE MAC ethernet, to determine whether the data is arrived successfully, else you may try to perform a MAC loopback test to investigate.