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Honored Contributor I

Multiple Masters at DDR2-HPC - Where is the problem?



In my design there are the following components connected to a singe DDR2-High-Performance-Controller: 

CPU -> pipelining bridge1 -> DDR2-HPC (writes to DDR2 only for one time at the beginning) 

TSE <- SGDMA1 <- pipelining bridge2 <- DDR2-HPC (reads from DDR2) 


Everything works fine... 


Now, I added and connected the following third component to DDR2-HPC: 

Streaming Source -> SGDMA2 -> pipelinging bridge3 -> DDR2-HPC 


After connecting this third component to DDR2-HPC the design doesn't work anymore. I didn't activate or do someting else with SGDMA2, but the design doesn't work anymore. This means, that there is no output Data at TSE. 


What could be the problem? 


Thanks for every hint! 


Best regards, 

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Honored Contributor I

Hi tonib, 


If you say the DDR2-HPC has stopped working, do you mean that you cannot access the DDR2 memory anymore - not even from you processor? Or is it only the TSE output that has seized? 


Are you sure you have not changed anything else in your design? One way to check is to just disable the new components in SoPC-Builder and to regenerate and compile. Have you changed any of the address ranges for the pipelined bridges maybe? Are you still making timing - adding another master to the HPC slave interface might reduce your fmax and maybe you are now running at too high a clock frequency causing unpredictable failure? 


You could also use SignalTap to look at the signals between the DDR2-HPC and SGDMA1 and SGDMA2 to see what is going on. 


That is all I can guess at for the moment....