FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5990 Discussions

Multiple (concatenated) DDR3 interface

Altera_Forum
Honored Contributor II
764 Views

Hello - 

 

I am looking to design a DDR3 controller that interfaces to two 16-bit wide DDR3 memory devices as one 32-bit interface. On our board we plan to share address and control lines for the two devices, but each device would have their own DQ, DQS and DM signals.  

 

I was looking at DDR3 Uniphy SDRAM controller's Ping Pong PHY architecture, but I do not think I want that, as it looks like it time multiplexes transactions between the two devices. We need 64-bits (2 * 2*16 bits) of data written on one memory clock, not across two clock cycles.  

 

I attempted to build the DDR3 controller core using presets for our memory device, and just change the width from 16 to 32 bits. It looked like it changed the DQS and DM outputs from the core correctly, but then I realized that the calibration data from each 16-bit DDR3 device would be replicated twice on the aggregate 32-bit bus, and I doubt the one controller core would know how to handle that. 

 

What I was thinking of doing was create a master and a slave core and encase them in a wrapper. The Master would share its PLL/DLL/OCT with the slave. The master core would drive both device's control, clock, clock enable signals, but each core would drive their own DQ, DQS, and DM signals. 

 

Any reasons why that couldn't work? 

 

Thanks.
0 Kudos
0 Replies
Reply