Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
2,484 Views

NIOS TSE initialize

Dear All, 

 

I am new in NIOSII and TSE. I use the Altera developemnt DK-DEV-4CGX150N for project development. I use the Qsys to build up my system and want to write some code to make the development board to TX some data to my PC. 

 

I use a sniffer program to capture the data TX to my PC. In my current situation, I cannot receive any data at the PC. My program flow is as below: 

1. Hardware reset the PHY. 

2. Initialize the phy (mdio address, change to RGMII mode...) 

3. Software reset the TSE 

4. Setup those FIFO threshold of the TSE 

5. Disable both shift 16 for TX and RX 

6. Set the TSE CMD config to enable the TSE 

7. Set the MAC address of TSE 

8. Set up SGDMA device and descriptor 

9. Send data to my PC. 

 

I reference to the examplet program in following thread to build my program. But still not work. 

 

"tse mac and marvell 88e1111

 

I attached herewith is a few files of my design for your refrence. 

 

I believe that the issue is due to the initialize process of my TSE and phy. Would any one provide some advice on it. 

 

Thanks for your kind help in advance. 

 

Best Regards, 

Albert Siu
0 Kudos
23 Replies
Altera_Forum
Honored Contributor I
150 Views

The 88E1111 has a bug of reset, so You need to do a hardware reset for certain amount of time before initialization. E.g. do a running out 16bit counter. 

 

Also did You add proper commands for RGMII initialization in Nios? Take the file from example projects. It's called tse_my_system.c afaik.
Altera_Forum
Honored Contributor I
150 Views

OriginallyI perfrom the hardware reset in the following way. 

1. Pull the reset pin of phy low 

2. sleep for 10 ms by usleep (10000) function 

3. Push the reset pin of phy high 

4. Initialize the phy 

 

I change to the following but still not work 

1. Pull the reset pin of phy low 

2. sleep for 10 s by usleep (10000000) 

3. Push the reset pin of phy high 

4. sleep to 10 s by usleep (10000000) 

5. Initialize the phy 

 

The function eth_hw_rst is use to perfrom the hardware reset all those sleep and push reset pin high or low perform wihtin this function. 

 

Then I call the function eth_phy_init to initialize my phy. Within this function I perform the following 

1. Set the MDIO address by IOWR_ALTERA_TSEMAC_MDIO_ADDR0 (tse_mac.base, 0x12); 

2. Change to RGMII mode by IOWR_ALTERA_TSEMAC_MDIO (tse_mac.base, 0x12, 0x1B, (tem_data | 0x0B)); 

3. Enable RGMII timing control by IOWR_ALTERA_TSEMAC_MDIO (tse_mac.base, 0x12, 0x14, tem_data); 

4. Reset the physical device IOWR_ALTERA_TSEMAC_MDIO (tse_mac.base, 0x12, 0, (tem_data | PCS_CTL_sw_reset)); 

 

Then I initialize those TSE IP. 

 

I am not sure whether there is any error in my initialize process. Please provide some advice. 

 

BTW. I open the tse_my_system.c file it only the following command. 

alt_tse_system_info tse_mac_device[MAXNETS] = { 

TSE_SYSTEM_EXT_MEM_NO_SHARED_FIFO(ETHERNET_SUBSYSTEM_TSE_MAC, 0, ETHERNET_SUBSYSTEM_SGDMA_TX, ETHERNET_SUBSYSTEM_SGDMA_RX, TSE_PHY_AUTO_ADDRESS, &marvell_cfg_rgmii, ETHERNET_SUBSYSTEM_DESCRIPTOR_MEMORY) 

 

Do you mean I need to add this command in my program flow. 

 

But I do not use those inchestack also have not call those alt_tse_* function call
Altera_Forum
Honored Contributor I
150 Views

Firstly run the example Simple Socket Server RGMII. It has that file already in the project so it should run WITHOUT ANY CHANGES.

Altera_Forum
Honored Contributor I
150 Views

I try to create a new project with the simple socket server (rgmii) template. But I cannot download it to my development board for debug. I use the SOPC file gerneate from the Altera reference project tripple speed ethernet reference design (with proper I/O and device mapping). 

 

I also try to trace those source code of this newly create project, but I cannot find any information on how to initialize my PHY. 

 

Also the simple socket server use OS and inchestack, but I target not to use the OS also build our own stack. Although I will continue to trace the source code of the simple socket server (RGMII), I feel I still need a huge amount of effort to fix my issue. 

 

So if any one can guide me on how to initialize the 88E1111 please provide some infomraiton for me to continue writing my code, testing and debuging. 

 

Thx.
Altera_Forum
Honored Contributor I
150 Views

I finially can TX data from my development board to my PC but there is soomthing strange. 

 

PC MAC address: 00-1B-21-51-D3-C8 

Development MAC address : 02-03-04-05-06-07 

 

The packet receive @PC view by sniffer 

Destination MAC: 00-1B-21-51-D3-02 

Source MAC: 03-04-05-06-07-07 

 

All other data in the packet are correct. 

 

The data buffer that SGDMA need to TX is 

00 1B 21 51 

D3 C8 02 03 

04 05 06 07 

.... 

 

The address of this buffer is 0x0004EC2C 

 

One thing I am not sure is whether the address of my buffer is 32-bit allign. Or in other word, I would like to have more idea on how to check whether my data buffer is 32-bit align. Since SGDMA need to access data in 32-bit align format. 

 

BTW. if anyone have idea on the strange condition of my source and destination MAC address. Please provide some advice to me. 

 

Thx.
Altera_Forum
Honored Contributor I
150 Views

Upload a picture of TSE MAC configuration window. Did You enable packet alignment there?

Altera_Forum
Honored Contributor I
150 Views

I enable packet alignment (as per the screen capture) in the IP setup wizard. 

 

I also disable bothe TX and RX shift 16 in the program by the following function. 

 

IOWR_ALTERA_TSEMAC_TX_CMD_STAT (tse_mac.base,  

(result & (~ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK)));  

 

IOWR_ALTERA_TSEMAC_RX_CMD_STAT (tse_mac.base,  

(result & (~ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK)));
Altera_Forum
Honored Contributor I
150 Views

 

--- Quote Start ---  

 

I also disable bothe TX and RX shift 16 in the program by the following function. 

 

IOWR_ALTERA_TSEMAC_TX_CMD_STAT (tse_mac.base,  

(result & (~ALTERA_TSEMAC_TX_CMD_STAT_TXSHIFT16_MSK)));  

 

IOWR_ALTERA_TSEMAC_RX_CMD_STAT (tse_mac.base,  

(result & (~ALTERA_TSEMAC_RX_CMD_STAT_RXSHIFT16_MSK))); 

--- Quote End ---  

 

 

 

You don't need these. Leave the code as is, without any modifications. It should work fine.
Altera_Forum
Honored Contributor I
150 Views

After comment out these two code the result is different (I consider this case is more worst than the origianl one). 

 

The packet size I receive is only 76 bytes instead of 78 bytes (which is the total data size I intend to send from development board to PC). 

 

The MAC address is as below: 

Destination address: 21-51-d3-c8-02-03 

Source address: 02-03-04-05-06-07 

 

BTW. If I setup the configure register as the following. Is it true that the TSE will use the MAC address that I program into the TSE register with the location where contain the source MAC address at my original data buffer. 

 

result = ALTERA_TSEMAC_CMD_TX_ENA_MSK | 

ALTERA_TSEMAC_CMD_RX_ENA_MSK | 

ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK | 

ALTERA_TSEMAC_CMD_TX_ADDR_INS_MSK | 

ALTERA_TSEMAC_CMD_RX_ERR_DISC_MSK; 

 

IOWR_ALTERA_TSEMAC_CMD_CONFIG (tse_mac.base, 

result);
Altera_Forum
Honored Contributor I
150 Views

Actually, I don't understand why You first don't want to run example projects, like Simple Socket Server and check if the hardware configuration is OK?

Altera_Forum
Honored Contributor I
150 Views

I understand that those reference design can help me to understand on how to control the TSE. But I cannot download it to my development board after I compile it on the NIOS SBT (I can sure I already program the FPGA with proper sof file). 

 

Also I cannot find those code for initialize the TSE within the simple socket server example. The example use UCOS and nichestack. And it call some UCOS function to initialize the system but I cannot view the code in detail. 

 

Another major concern is both of them is not free of charge, so I intend not to use both of them.
Altera_Forum
Honored Contributor I
150 Views

Try to run the example first. If it runs fine, then You can test Your own design.

Altera_Forum
Honored Contributor I
150 Views

I agree with Socrates. Begin with a configuration that works and go from there. Both the TSE and the PHY must be initialized properly and it's better to be sure that your hardware configuration and FPGA image work properly before looking into the software. 

What do you mean by "I cannot download it to my development board"?
Altera_Forum
Honored Contributor I
150 Views

I try to use debug as -> NIOS II hardware to download the reference design to my development board for testing. Sometime later NIOS SBT pop up a window and indicate that I cannot download the elf into my development board. 

 

I can downlaod some simple self design program to control LED on the board.
Altera_Forum
Honored Contributor I
150 Views

What is the *exact* error message?

Altera_Forum
Honored Contributor I
150 Views

SBT report "Downloading ELF process fail". As per the screen capture. 

 

The same error message appear even I reboot my PC.
Altera_Forum
Honored Contributor I
150 Views

We need to see what's going on in the console when you try to upload the software in the FPGA, it will tell more where the problem is coming from. 

Are you sure you uploaded the correct configuration in the FPGA first?
Altera_Forum
Honored Contributor I
150 Views

I can sure I download the correct FPGA configuration into my development board. Is there any method for me to counter check against this?

Altera_Forum
Honored Contributor I
150 Views

If You are not able to paste console output to the pastebin and paste link here, how can You be sure You are able to download the design at all?!

Altera_Forum
Honored Contributor I
46 Views

Attached is the screen capture when I choice debug as in NIOS SBT. I do not capture the screen of Quartus II programmer. As it report 100% download success in that process. Please let me knwon if more information is required for fixing my issue. Thx.

Reply