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Altera_Forum
Honored Contributor I
797 Views

NIOS2 to 8 bit MM slave block data transfer -- Help

Hi,  

 

I Have a 8bit addressed , 8bit width FIR IP module which i want to interface with NIOS2.  

 

My Module is interfaced with  

 

1. MM Slave Interface 2. Interrupt Sender 3. Clk input.  

 

Entity module_fir is 

PORT( 

avalon_slave_reset:IN STD_LOGIC; 

avalon_slave_address:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 

avalon_slave_chipselect:IN STD_LOGIC; 

avalon_slave_clk:IN STD_LOGIC; 

avalon_slave_read:IN STD_LOGIC; 

avalon_slave_write:IN STD_LOGIC; 

avalon_slave_writedata:IN STD_LOGIC_VECTOR(7 DOWNTO 0); 

avalon_slave_readdata:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); 

avalon_slave_FIR_Completed:OUT STD_LOGIC 

); 

end module_fir; 

 

I am using a MM slave interface with Native addressing, which s giving me Address mapped from 0x9000 to 0x93ff to my slave.  

the Control Register of the my slave needs to be addressed as 0x0111_1100 to start my processing.  

 

Though i am trying to write the as  

 

IOWR_8DIRECT(FIR_INTERRUPT_0_BASE, 0x1F0, 0x03) ; 

 

to receive the value as below,  

 

if avalon_slave_address = "01111100" then 

control_reg_value <= avalon_slave_writedata; 

 

 

data is not received at the HW end.  

 

PLease help .
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4 Replies
Altera_Forum
Honored Contributor I
64 Views

Use signaltap probes on the Avalon signals received on your slave to see how this IOWR translates into signals on the avalon slave interface. 

I personally stopped using non 32-bit slaves a long time ago, it gives too many headakes ;). I find it much easier to always use a 32-bit data bus, even if it means ignoring the top 24 bits. I know this is what native addressing is also supposed to do, but I lost a lot of time on this mode. Besides, I think it's deprecated in QSys anyway, so it could be a good idea to stop using it. 

Did you try to use a IOWR_32DIRECT macro instead? It shouldn't make any difference in theory, but you never know...
Altera_Forum
Honored Contributor I
64 Views

I think your offset is wrong. 0x1F0 is "1 1111 0000" in binary which doesn't fit in your 8 bits of 1-byte addresses. I think you want to do this instead if I understand your addressing scheme: 

 

IOWR_8DIRECT(FIR_INTERRUPT_0_BASE, 0x7C, 0x03);
Altera_Forum
Honored Contributor I
64 Views

Wouldn't this apply only if dynamic bus sizing were used instead of native addressing? 

The component's address span is 0x3ff, which seems to show that each 8-bit register is mapped to a 32-bit word. 

But as I said I stopped using native or dynamic bus sizing a while ago...
Altera_Forum
Honored Contributor I
64 Views

Ooops yes you are correct, I didn't see that part of his post. 

 

What happens if you do this instead? IOWR(FIR_INTERRUPT_0_BASE, 0x7C, 0x3) 

 

Also which tool are you using? SOPC Builder or Qsys? The behavior accessing native slaves is slightly different between the two tools depending on the data width of the master and slave.
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