I am aware that Arria 10 native PHY does not support SSC (spread spectrum clocking) for any custom protocols.
I am targeting to implement a custom protocol which needs SSC in the transceiver on transmitter side. I am planning to use a SSC enabled clock as the reference frequency with SSC_DOWN_SPREAD_RATE of 30 to 33KHz & SSC_DOWN_SPREAD_RANGE of 0.4 to 0.5%.
IF I provide the reference clock with downspread, whether Transceiver/ATX PLL will have any issue wrt the functionality & stability?
Also, whether this is the proper way to implement SSC in transmitter side? (We are not worried about the consequences of SSC on the receiver side of Arria 10 transceiver)
As I understand it, you would like to feed refclk with SSC for the A10 TX. You are not concern about the ppm violation at the A10 RX side. For your information, if you can ensure that the SSC is within the datasheet spec of "Spread-spectrum modulating clock frequency" and "Spread-spectrum downspread" for PCIe mode, there should be no issue with the TX and ATX PLL. I observe your specs seems to be within the specs. Note that you should perform thorough validation to ensure the functionality is meeting your expectation since using SSC for non-PCIe mode is something not validated and not a normal supported feature.
Please let me know if there is any concern. Thank you.
That means I can connect SSC enabled clock to Transceiver reference clock, but the clock's frequency variation must be within +/-300ppm wrt specified frequency.
(for example, 156.25MHz +/- 300ppm, this varied ppm can be due to SSC down-spreading )
I believe the initial inquiry has been addressed. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.