Sirs,I am learning transceiver matters and want to play with ethernet packets for starters. My board is Arria II GX (EP2AGX260FF35I3) and it has 10/100/1000 Ethernet out of the box. I figured that it comes with Marvell 88E1111 PHY that provides RGMII interface (took me few ours to get what RGMII is for :-)). So after poking around a little bit I came across Triple Speed Ethernet core that can work with it. Thus far I was able to instantiate it, hook up my sink for TX buffer and hookup wiring of the TSE with RGMII. I don't know how to handle MDIO yet, so it is connected to GND. As you can guess.. nothing works. Nothing is coming down from TX buffer, LINK leds on the boards are off etc. I am pretty much a newbie in this matter and I need your help to figure it out. I have a feeling that I need to write a PHY controller that will set up PHY by sending control commands to its configuration registers (at least MAC address?). Is that true? Is there a way to bypass that somehow (i.e. use some default PHY configuration)? If not, I would appreciate if you could send me in a right direction (some examples would help a lot indeed). Also, will a regular WIFI router forward any packets to my PHY so that I can receive it from TSE TX buffer or router does something smart about it, or perhaps MAC will reject/drop those packets? Or should I plug the other end of a cable into my PC and forcefully generate some signals/traffic? Please note that I am not using Nios and don't have a soft CPU. I am trying to teach myself basics and avoid using high-level stuff where everything is done for you. If that helps, here is my verilog piece of crap that could as well be a problem:
module top ( // General I/O. input ref_clk, // 125.00 MHz LVDS TOP Clock input user_pb, // 1.8V (TR=0) output user_led, // 2.5V active low // Ethernet 10/100/1000 RGMII. output enet_gtx_clk, // 2.5V RGMII Transmit Clock output enet_tx_d, // 2.5V TX to PHY input enet_rx_d, // 2.5V RX from PHY output enet_tx_en, // 2.5V RGMII Transmit Control input enet_rx_clk, // 2.5V Derived Received Clock input enet_rx_dv, // 2.5V RGMII Receive Control output enet_resetn, // 2.5V Reset to PHY (TR=0) output enet_mdc, // 2.5V MDIO Control (TR=0) inout enet_mdio, // 2.5V MDIO Data (TR=0) input enet_intn // 2.5V MDIO Interrupt (TR=0) ); wire reset = ~user_pb; wire tse_set_1G_mode = 1; // Gigabit mode selection. wire rx_data; wire rx_data_valid; wire rx_ready = 1; // Always ready :) reg buffer = 0; reg buffer_state = 0; assign enet_gtx_clk = ref_clk; tse_eth tse(.rx_clk(enet_rx_clk), .tx_clk(ref_clk), .reset(reset), .rgmii_in(enet_rx_d), .rx_control(enet_rx_dv), .rgmii_out(enet_tx_d), .tx_control(enet_tx_en), .set_1000(tse_set_1G_mode), .ff_tx_rdy(rx_ready), .ff_rx_data(rx_data), .ff_rx_dval(rx_data_valid)); always @ (posedge ref_clk or posedge reset or posedge rx_data_valid) begin if (reset) begin buffer <= 0; buffer_state <= 0; end else begin if (rx_data_valid) begin buffer <= buffer; buffer <= rx_data; buffer_state <= buffer_state; buffer_state <= 1'b1; end else begin buffer <= 0; buffer_state <= 0; end end end assign user_led = ~buffer_state; assign user_led = ~buffer_state; assign user_led = ~reset; assign user_led = ~reset; // Light up only when reset is asserted. endmodule("tse_eth" is a top module of TSE core generated by IP wizard) Any help is highly appreciated. Thank you!
Problem solved. I found a TSE reference design here (https://www.altera.com/support/software/download/refdesigns/ip/interface/dnl-ref-tse-phy-chip.jsp). It is not using Nios and is targeting Arria II family device. Quartus II opens archive file, everything synthesizes and works out of the box.