FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5984 Discussions

New credit signals on Stratix V PCIe Hard IP

Altera_Forum
Honored Contributor II
804 Views

Anyone tried using the new signals for dealign with credits on the Stratix V Hard IP? The manual Stratix V Hard IP for PCI Express version 11.0 explains the new signals but does not explain how to use them. 

 

There are the busses: tx_cred_datafccp, tx_cred_datafcnp, tx_cred_datafcp, tx_cred_hdrfccp, tx_cred_hdrfcnp, tx_cred_hdrfcp. They are for indicating the credit limit. I presume they are static but the manual does not state anything. 

 

Then there is tx_cred_fchipcons, that is 6 bits wide and is supposed to return a pulse when a credit is consumed by the Hard IP and it has one bit per type. Sounds nice, but the comment states "During a single cycle, the IP core can consume either a single 

header credit or both a header and a data credit.". But if you configure the Hard IP for say Gen3, 256bit bus and multiple packets per cycle, you could potentially have two header credits consumed in one cycle or two data credits consumed in one cycle. 

The question comes up if there is an error in the manual and there is a missing second set of tx_cred_fchipcons or perhaps if a pulse indicates that credits of a type  

 

There is plenty to read out there on the ko_cpl_spc_header and ko_cpl_spc_data busses, but these others there is almost nothing written. 

 

Thanks, 

 

Glenn
0 Kudos
0 Replies
Reply