Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
719 Views

New library using DSP Builder standard blockset

I have created new blocks inside a new library using DSP Builder standard blockset. 

 

I have created and simulated a new model using these library and its blocks, but when I compiled the model the DSP Builder has created only simple VHDL project. I have opened the project at Quartus II and It is very small. The blocks wasn't compiled. I can't compile each block or full library because the compiler show one error. 

 

What could be wrong?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
35 Views

Dear, 

 

In my model the ROM was data input and DRAM was data output. It didn't have explicit inputs and outputs. When It was compiled It was only created two inputs: clock and areset, but any output. 

 

Please, don't ask me about why I did it. I have changed my model and now it is more professional, have better interface with outside world. 

 

Thank you all.
Altera_Forum
Honored Contributor I
35 Views

Dear, 

 

In my model the ROM was data input and DRAM was data output. It didn't have explicit inputs and outputs. When It was compiled It was only created two inputs: clock and areset, but any output. 

 

Please, don't ask me about why I did it. I have changed my model and now it is more professional, have better interface with outside world. 

 

Thank you all.
Reply