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Altera_Forum
Honored Contributor I
912 Views

Nios II interfering with VGA Data

Hi!  

 

I'm trying to implement a Nios II core to manage an RS232 link on a Cyclone IV embedded in a DE2-115 board. On the same FPGA, but unrelated to the Nios II, is a VGA controller writing data in real time from a digital camera to a monitor. I've gotten the VGA hardware working flawlessly on its own, but when I run the Nios II on the FPGA in the same project, it introduces a lot of corruption into the image. Note that I'm using an Altera generated RAM for the VGA's memory, but using the onboard SRAM to store program memory for the Nios II. I'm stumped to where this is coming from- any suggestions as to what I could do? 

 

Thanks very much.
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3 Replies
Altera_Forum
Honored Contributor I
30 Views

Is it just random pixels corrupted or does your output not work? If it's just a few bits here and there I would suspect it could be noise on the board causing this or a timing issue. Here is what I would do to tackle this: 

 

1) Make sure you have timing constraints, if you don't then all bets are off and you probably just got lucky the VGA only design worked. 

 

2) Remove the VGA portion of the design and make sure the Nios II portion actually works properly on it's own. 

 

3) Look at the pin locations of the VGA interface and see if there are other interfaces you are using nearby and start to try to narrow the problem down to potential noise issues like crosstalk.
Altera_Forum
Honored Contributor I
30 Views

There's clearly a functioning image; for some reason, however, there seem to be bands of semi-regular corruptions popping up in the final image. There are two main regions of corruptions that happen at regular spaced intervals (appears to be about every ten-fifteen pixels or so). As to the timing concerns, TimeQuest yielded an Fmax of 153 MHz- two to three times what I'm running at. I'll give your other suggestions a shot. Thanks for your help! 

 

Sorry to see the Habs didn't make it, by the way. Next year!
Altera_Forum
Honored Contributor I
30 Views

Actually I was thinking more along the lines of the off-chip timing between your VGA IP and the DAC. I would find the datasheet for the DAC and make sure you constrain that interface accordingly otherwise I would assuming random bits would be corrupt depending on the fitting results of your design. 

 

I'm not too bummed about the Habs this year, they get draft picks, hopefully some good management, Toronto missed again, ...... and if I'm lucky the Bruins will golfing soon too :)
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