FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
5741 Discussions

No matches for nodes in Signal Tap II even after fitter run

VenkateshSathar
New Contributor I
410 Views

What could be the reason or mistake I might have done for not getting any nets in signal tap to add and monitor even after the fitter ran.

 

Annotation 2019-07-03 102220.jpg

 

 

Anybody help me on this..?

 

It could be some obvious mistake but I couldn't able to find out. Help me.

0 Kudos
1 Solution
VenkateshSathar
New Contributor I
97 Views
1 Reply
VenkateshSathar
New Contributor I
98 Views
Reply