FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6020 Discussions

Not able modify testbench BFM Intel P tile PCIE avmm example design on Stratix 10DX device

10
Beginner
317 Views

 Hi all,

    I ran PCIE Gen4x16 ptile avmm example design while running it and I got the VCS report which i attach it.

In that report, I analyze the report and i noticed that "upstream component can't be backpressed".

I attach the snapshot of that 

can you please clarify the below questions:

       1.Testcase flow of PCIe BFM. How to execute different tests?(Which Modules need to look )
       2.Need procedure for Testing Memory write and Read (32- and 64-bit address) TLP's.
       3.How to configure the Descriptor for DMA modes(Write and Read) in PCIE RC BFM?
 
Thanks in Advance
Indirapriya
0 Kudos
1 Reply
Rahul_S_Intel1
Employee
250 Views

Hi Indira Priya ,

 Kindly find page no: 5 of the below document 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-dex-ptile-pcie-avmm.p...

Reply