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Not able to generate HDL because of tight clock constraints -Altera DSP builder

Honored Contributor II



My name is Wasim. I am using Altera DSP builder for designing a system for Altera Stratix IV FPGA. I am able to simulate the system in simulink but when I generate the hardware it says 'Failure to redistribute delay in [Channel_Est_Ind_dut_prim] - tight clock constraints'  

My clock is 150 MHz. 


I went through the user guide for Altera DSP builder advanced toolkit, it say if the design is not able to meet the timings then DSP builder will add additional pipeline stages and try to meet the timing with given clock signal. I dont understand why it is not adding the pipeline stages and generate the hardware? Is there any setting I am missing? My design is simple single channel design.  


I am attaching the screen shot of the error and clock settings.
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Honored Contributor II

Can we see a screenshot of your design? This is usually caused by you having a loop without enough delay around it to meet your desired clock speed.

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