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PCI Express Avalon ST transmit with breaks in data flow

Altera_Forum
Honored Contributor II
848 Views

Hi all, 

 

I ran into a problem here when using the Stratix IV GX Hard IP. I start sending a packet to the IP using the TX channel Avalon-ST. As specified in the Avalon-ST spec, a valid cycle is indicated by the Valid signal high. I noticed though once the first cycle with the SOP high has been sent, the IP continues to latch in cycles even in cycles when valid is not high. You can see that because the fifo write pointer from the IP keeps incrementing independantly of the valid signal high or low. The IP hangs then, probably in an undefined state. 

 

This sounded to me a bit odd, but perhaps once the SOP has been sent, a series of valid cycles with no interruption has to be given until the EOP arrives. 

 

Anyone know something about this or perhaps has experienced this before? Being the PCI Express standard does require a contiguous flow it could be that the IP requires that as well on the TX channel, but I did not see that stated in the IP spec.
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3 Replies
Altera_Forum
Honored Contributor II
91 Views
Altera_Forum
Honored Contributor II
91 Views

Thanks for the response. I was suspecting something like this. It would be nice if the documentation stated it more clearly in the tx_st_valid signal description.

Altera_Forum
Honored Contributor II
91 Views

I 100%ly agree. And I don’t understand why this feature is not supported by Antera – most other PCIe IP vendors do support this, or even allow to differentiate between a buffered transaction that allows this signal to be de-asserted arbitrarily, and an unbuffered transaction that behaves as required by Altera.

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