PCI Express + Hard IP + Cyclone IV GX: DMA test stalls (with both Verilog and VHDL)

[Altera_Forum]

Software: Quartus II 9.1 SP2 + ModelSim-Altera V6.5b SE 

 I've followed the online PCI Express course ("PCI Express Hard IP Quick Start Guide with SOPC Builder") to use SOPC Builder to create a system with a PCI Express Hard IP core + DMA controller + online RAM. This course is essentially the same as chapter 8 of the PCI Express user guide pdf. I've tried both VHDL and Verilog.   Firstly, with a Cyclone IV GX device selected (instead of the recommended Stratix IV), the VHDL version appears to require the following addition to "setup_sim.do" (just after "alias s "_init_setup") before the simulation will run in ModelSim or vsim:    vcom -93 -explicit c:/altera/91sp2/quartus/eda/sim_lib/cycloneiv_hssi_components.vhd vcom -93 -explicit c:/altera/91sp2/quartus/eda/sim_lib/cycloneiv_hssi_atoms.vhd vcom -93 -explicit c:/altera/91sp2/quartus/eda/sim_lib/cycloneiv_pcie_hip_components.vhd vcom -93 -explicit c:/altera/91sp2/quartus/eda/sim_lib/cycloneiv_pcie_hip_atoms.vhd    [BTW: Should I report this problem to Altera?]   Having fixed this, the test runs, sets up the BARs, performs a RAM write and read test (which passes), then stalls during the DMA test.   Looking at the waveforms in Wave, during the DMA test the DMA appears to perform a read-write data transfer between 49 us and 55 us and then asserts dma_0_control_port_slave_irq.   However the "wait until ( INTA='1')" statement in "altpcietb_bfm_driver.vhd" does not appear to complete, hence the stall.   The same happens with both VHDL and Verilog versions of the design.   What might be causing this and/or how can I diagnose further?    I can't change the device to an Arria II or Stratix IV device (to see whether the tutorial works unmodified) as I have only the Web Edition of Quartus II.   I've attached the transcript in case it is helpful.   JB   PS: I'm new to these tools (6 days) so please forgive any "beginner" type errors or clumsiness!