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Valued Contributor III
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PCI Express IP Hard core reference clk

Hi, 

 

I'm implementing PCI Express in Cyclone 5 GX and I have a question - I'm using lane 0 therefore TX and RX are connected to GXB_RX_L0 and GXB_TX_L0, but due to the pcb routing I can't connect reference clock to REFCLKL0. Instead it can be connected to REFCLKL1. Does it have any influence on the work of PCIE? 

Other thing - can I have a REFCLK slower than 100/125 MHz? 

 

Best regards, 

Dominik
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Valued Contributor III
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REFCLK has to be exactly 100Mhz, or exactly 125Mhz, with fairly tight jitter margins. You select which when you parametrise the core, which selects the fixed ratio between REFCLK and the data clock. You should be using the same clock source (crystal, whatever) for both the to the root port and slave - the phase relationship needs to be constant over time. You normally carry the refclock alongside the data lanes, not generate it locally (otherwise your frequency/phase is not going to match the other source).  

 

For using REFCLKL1, I would just assign that pin to be your refclk, set the part correctly and see if the fitter gives you an error. It will know if the HSSI clock mux settings cover this arrangement better than we do.
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Valued Contributor III
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Hi shuckc, 

 

Thanks, the link is up now (ltssmstate = L0) but still don't see any data going out from hard IP core. How can I debug and see whether anything is coming to Hard IP and/or get discarded?  

 

Best regards, 

Dominik
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Valued Contributor III
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Are you using the QSYS generated Core, and which varient if you are (streaming, or MM)? I've only worked with the QSYS-MM PCIe core. 

 

Is your root port a computer or another FPGA?
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Valued Contributor III
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Yes, I'm using QSYS generated core - version MM. Fpga (endpoint) is connected to Keystone processor from TI. The external loopback on processor (as a root) is working so I wonder what goes wrong. 

 

Dominik
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Valued Contributor III
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I wouldn't expect to see anything further from L0 until the operating system on the Keystone probes the PCIe bus to enumerate devices. Do you have e.g. a Linux install and access to /sbin/lspci or similar? The device should show up as enumerated with the device/vendor codes you specified in the core. Actually generating read/write transactions from the host requires you either write a device driver or use Dave's excellent PCI pci_debug tool to access the bar memory space via. /sys/ filesystem. 

 

It's in the zip file you can download from Dave's post, needs a c compiler and make on the host. http://www.alteraforum.com/forum/showthread.php?t=35678
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