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Altera_Forum
Honored Contributor I
1,063 Views

PCI Express to external memory interface.

Hi There, 

 

I am working to access external memory (DDR2) using pci express, i took a reference design from http://www.alterawiki.com/wiki/pci_express_in_qsys_example_designs and prepared design for my board (cyclone V- 5CGTFD5C5U19A7) and successfully simulate the design for data read write and verify it. 

 

But when i am testing the design on board i get nothing in the device manager. 

 

In the reference design's top module i found LED logic as below,  

 

always @(posedge pld_clk_clk or negedge any_rstn_rr) 

begin 

if (any_rstn_rr == 0) 

begin 

alive_cnt <= 0; 

alive_led <= 0; 

comp_led <= 0; 

L0_led <= 0; 

gen2_led <= 0; 

lane_active_led[3:0] <= 0; 

end 

else 

begin 

alive_cnt <= alive_cnt +1; 

alive_led <= alive_cnt[24]; 

comp_led <= ~(ltssm[4 : 0] == 5'b00011); 

L0_led <= ~(ltssm[4 : 0] == 5'b01111); 

gen2_led <= ~gen2_speed; 

end 

end 

 

I get continuously 1'b0 on compl_led,L0_led, and ltssm is stuck in state 0 (6'b0- in signal tap). 

 

could anybody please tell me what is the ltssm state after reset de-asserted and when leds (Comp_LED,L0_led) glow and when not. 

 

Regards, 

Hitesh.
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2 Replies
Altera_Forum
Honored Contributor I
25 Views

Hi all, 

 

My ltssm state is swap between state-0 (6'b0) and state-1(6'b1). 

 

Could anybody tell me about why this happen and how to debug pcie. 

 

Will waiting for your reply. 

 

Thanking you, 

Hitesh.
Altera_Forum
Honored Contributor I
25 Views

LTSSM toggles between state 0x00 and 0x01 indicates the link fails the Receiver Detect sequence. 

Ensure your PCIe Tx lane has a capacitor value that is between of 0.075&#956;F–0.265 &#956;F. Normally people uses a 0.1uF cap.