FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.

PCI Pipe

Altera_Forum
Honored Contributor II
776 Views

I'm working on a PCIe design for a Stratix IV GX. I've instantiated the hardcore but I'm confused as to what I should do with all the PIPE signals. I'll be using the Altera transceivers. I've set the pipe_mode to "0" which indicates serial mode so are all the PIPE signals don't care? 

 

Andy
0 Kudos
0 Replies
Reply