FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
6223 Discussions

PCI Pipe

Altera_Forum
Honored Contributor II
‎12-21-2010 08:28 PM
849 Views

I'm working on a PCIe design for a Stratix IV GX. I've instantiated the hardcore but I'm confused as to what I should do with all the PIPE signals. I'll be using the Altera transceivers. I've set the pipe_mode to "0" which indicates serial mode so are all the PIPE signals don't care? 

 

Andy
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.